1. Field of the Invention
The present invention relates to a semiconductor memory device such as DRAM (Dynamic Random Access Memory). In particular, the present invention relates to an output circuit for a semiconductor memory device that makes it possible to achieve both a reduction in leakage current when the device is on standby and a reduction in current consumption when the device is active, and to a data output method for using with this output circuit for a semiconductor memory device.
Priority is claimed on Japanese Patent Application No. 2007-139104, filed May 25, 2007, the contents of which are incorporated herein by reference.
2. Description of Related Art
In order to reduce current consumption in a system, in particular, an ASIC (Application Specific Integrated Circuit) chip has been developed in which a reduction in the operating voltage has been achieved. In contrast, in DRAM, due to the need to secure operations of the memory cell portion, it is difficult to achieve a reduction in voltage compared with an ASIC which is a simple logic circuit. When the development periods of DRAM and ASIC are the same, the DRAM typically requires a higher operating voltage than that of the ASIC chip.
FIG. 8 is a block diagram showing a system 1 for a recent mobile device in which DRAM has been mounted, with only that portion which is concerned with the present invention being shown. The system (i.e., a DRAM equipped system) 1 shown in FIG. 8 has an ASIC chip 10, and a DRAM (i.e., a DRAM chip) 20 that is used as a memory section for the ASIC chip 10. The ASIC chip 10 and a DRAM core circuit section 21 inside the DRAM 20 are connected via a data input/output circuit section 30 by means of two-way data lines DQ0 to DQn.
The respective data lines DQ0 to DQn and the ASIC chip 10 are connected by ASIC side drivers (i.e., line drivers) 11 and ASIC side receivers (i.e., line receivers) 12. The respective data lines DQ0 to DQn and the data input/output circuit section 30 inside the DRAM chip 20 are connected by output circuits 31 and input circuits 32.
Using the above described structure, the ASIC chip 10 performs the writing and reading of data on the DRAM 20 through the two-way data lines DQ0 to DQn.
As is shown in FIG. 8, while power supply voltage of 1.2V (VDDA) is supplied to the ASIC chip 10, power supply voltage of 1.8V (VDD) is supplied to the DRAM chip 20. Because of this, the voltage that is used at the interface between the DRAM chip 20 and the ASIC chip 10 needs to be 1.2V for the reasons explained below. Note that this interface is formed by the data input/output circuit section 30.
The first reason is that because the transistors used in the ASIC chip 10 have been optimized to 1.2V operation, it is necessary from the standpoint of gate breakdown voltage for the power supply voltage to be 1.2V or less. The second reason is that by lowering the voltage of the interface between the ASIC chip 10 and the DRAM 20 also to 1.2V, it is possible to curtail the current consumption of the system. Accordingly, in this system, the voltage VDDQ that is supplied to the output circuit 31 of the DRAM is 1.2V, which is a lower voltage than the voltage VDD of 1.8V that is supplied to the DRAM core circuit section 21. Namely, in the DRAM 20, it is only necessary for the output circuit 31 to operate at 1.2V. Here, in order to lower the operating voltage of the circuit, it is necessary for the threshold voltage of the transistors inside the circuit to be lowered. However, if the threshold voltage is lowered, the problem arises that there is an increase in leakage current when the transistors are OFF, and current consumption when the device is on standby increases. A specific example of the output circuit 31 is given below to illustrate this problem.
FIG. 9 is a diagram showing the circuit structure of the conventional DRAM output circuit shown in FIG. 8. In the output circuit shown in FIG. 9, a data reading signal OUTHB from a memory cell (not shown) is converted into a signal OUTH by an inverter that is formed by a PMOS transistor Q101 and an NMOS transistor Q201. The signal OUTH forms a gate signal of a PMOS transistor Q501 for a high signal output. In addition, a data reading signal OUTLB from the memory cell is converted into a signal OUTL by an inverter that is formed by a PMOS transistor Q301 and an NMOS transistor Q401. The signal OUTL forms a gate signal of an NMOS transistor Q601 for a low signal output. A source terminal of the PMOS transistor Q501 is connected to the power supply VDDQ, while a drain terminal thereof is connected to a drain terminal of the NMOS transistor Q601. A source terminal of the NMOS transistor Q601 is connected to VSS. An output signal DQ is output from a connection point between the NMOS transistor Q501 and the NMOS transistor Q601. Note that, in FIG. 9, the PMOS transistors Q101, Q301, and Q501 that are surrounded by dotted lines are low threshold (Low Vt) type PMOS transistors.
In the DRAM output circuit 31 having the above described structure, in order to make it possible for operations to be performed at the low voltage of the power supply VDDQ (i.e., 1.2V), it is necessary to lower the threshold voltage (Vt) of the PMOS transistors Q101, Q301, and Q501 approximately 0.4V from the 1.8V at which the PMOS transistors are used. Typically, because the leakage current when the transistor is OFF increases by one decimal place when the threshold voltage is lowered by 0.1V, the PMOS transistors Q101, Q301, and Q501 become transistors in which there is an increase in the OFF current of approximately four decimal places. In contrast, because the threshold voltage of the NMOS transistors is originally lower by 0.3V to 0.4V than that of the PMOS transistors, and because the OFF current is also reduced, not only are operations possible at the low voltage of 1.2V, but there is also no problem with leakage current. The only problem with leakage current is generated by PMOS transistors which are turned OFF when the device is on standby.
In order to illustrate this leakage current problem, a description is given below of a circuit operation with reference made to the timing chart shown in FIG. 10. Note that in the description given below, for example, the PMOS transistor Q101 is abbreviated to simply Q101.
The signals OUTHB and OUTLB that are input into the output circuit on standby (Standby) are at the levels of VSS and VDD respectively. Accordingly, Q101 is turned ON and the signal OUTH is at the VDDQ level, and Q501 is turned OFF. Moreover, Q301 is OFF and Q401 is ON, and the signal OUTL is at the level of VSS. Q601 is also OFF. Accordingly, the output from the output circuit 31 is in a Hi-z (i.e., high impedance) state.
Next, when an active command (ACT) is input into the DRAM via a command (CMD) input (see FIG. 8) in synchronization with a clock signal CLK, the DRAM core circuit section 21 changes to an active state (Active). In this state, data can be read by means of a read command (RED).
Next, when a read command (RED) is input in synchronization with the clock signal CLK, after two clocks, data is output to the output signal DQ that is connected to the output circuit.
Next, when both the signal OUTHB and the signal OUTLB are at VDD, the signals OUTH and OUTL are both at VSS, the Q501 is ON, the Q601 is OFF, and the output signal DQ at a VDDQ level is output.
Next, when both the signal OUTHB and the signal OUTLB are at VSS, the signals OUTH and OUTL are both at VDDQ, the Q501 is OFF, the Q601 is ON, and the output signal DQ at a VSS level is output.
Next, when a pre-charge command (PRE) is input in synchronization with the clock signal CLK, the DRAM core circuit section 21 once again changes to a standby state (Standby), and the signals OUTHB and OUTLB are respectively at the levels VSS and VDD. Because of this, Q501 and Q601 are both OFF, and the output from the output circuit 31 is in a Hi-z state.
When the device is active, because the operating current is far greater than the leakage current from the transistors, the leakage current does not create a problem. The PMOS transistors which are OFF when on standby are Q301 and Q501, which is a transistor used for output, however, the gate level of Q301 is at the 1.8V VDD level of the DRAM core circuit section 21, and is 0.6V higher than the source level 1.2V of Q301. Because leakage current from the PMOS transistors when they are OFF is suppressed when the gate voltage is higher than the source voltage, the OFF current is at a level at which it does not create any problems.
Leakage current becomes a problem on standby only in the case of Q501 which is used for output, however, because Q501 drives the wiring or the substrate wiring between the DRAM chip and the ASIC chip 10, comparatively large sized transistors are used, and leakage current of several microamperes or more is generated. Typically, because the number of output terminals DQ in a DRAM is from 36 to 72, leakage current in a range of several 100 microamperes to 1 milliamperes is generated in the DRAM overall.
As is shown in FIG. 8, leakage current flows from the output circuit 31 to the ASIC side driver circuit 11 and the ASIC side receiver 12, and is the current consumed by the system when the DRAM is on standby. Typically, because DRAM having lower current consumption when on standby is in demand for DRAM used in mobile applications, it is not possible to overlook leakage current from transistors on standby in an output circuit.
Here, by setting the gate level of a PMOS transistor higher than the source level, it is possible to set the level of OFF at a deeper level and thereby restrict leakage current from the PMOS transistor. FIG. 11 shows a circuit in which the power supply of the inverter section that drives the gates of the transistors that are used for output is altered from VDDQ to VDD. FIG. 12 shows a timing chart of an output circuit of the DRAM shown in FIG. 11.
In the circuit shown in FIG. 11, the voltage of the drain of Q101 in the circuit shown in FIG. 9 has been altered to VDD (1.8V), but the basic circuit structure and operations are the same as the circuit shown in FIG. 9. In the timing chart shown in FIG. 12 as well, the only point of variance from the timing chart shown in FIG. 10 is that the output voltage VDDQ (1.2V) of the signal OUTH has changed to VDD (1.8V), and the basic timing is the same. Accordingly, any redundant explanation is omitted.
When the circuit is altered to the output circuit shown in FIG. 11, because the gate level of Q501 on standby is VDD=1.8V, leakage current is suppressed, and the above described problem of an increase in the system current on standby is solved. However, as is described above, because the size of the outputting PMOS transistors is large, current charging and discharging at the gate takes place at the level of the power supply VDD (VDD=1.8V), and the fact that operating current in the DRAM overall ends up increasing approximately several tens of milliamperes creates a problem.
Note that the power supply driver device disclosed in Japanese Unexamined Patent Application, First Publication No. 2005-304218 (referred to below as Patent document 1) exists as an output circuit that is constructed so as to be suitable for low voltage operations. However, this power supply driver device is not one in which, without there being any increase in operating current, leakage current is suppressed when the device is on standby.
As has been described above, in a conventional output circuit for a semiconductor memory device, leakage current during standby is suppressed by setting the gate level of the PMOS transistors for output to the voltage level of the power supply VDD which is a higher voltage level than that of the power supply VDDQ which is supplied to the output circuit, however, on the other hand, the problem arises that there is an increase in current when the device is active.